(1) FIELD OF THE INVENTION
The invention provides a solution to the problem of interfacing CMOS circuits using 3.3 volt power supplies with circuits using 5.0 volt power supplies. The invention provides a simple circuit to provide full rail to rail output voltage swing and prevent the PN junctions in the isolation wells of metal oxide semiconductor field effect transistors from becoming forward biased.
(2) DESCRIPTION OF RELATED ART
As VLSI chip design migrates from 5 volt designs to lower voltage designs, such as 3.3 volts, interfacing components with different power supplies is an unavoidable issue. U.S. Pat. No. 4,782,250 to Adams et al, U.S. Pat. No. 4,963,766 to Lundberg, U.S. Pat. No. 5,300,835 to Assar et al, U.S. Pat. No. 5,381,059 to Douglas, and U.S. Pat. No. 5,396,128 to Dunning et al all address the problem of interfacing a CMOS output buffer with higher voltage external circuits. However, these inventions offer solutions having more complex circuit designs than the circuits of this invention.
This invention provides a solution to the problem of interfacing with higher voltage external circuits which uses simple and inexpensive circuits.